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toshiba toshiba corporation 1/14 tlcs-90 series tmp90c800/801 the information contained here is subject to change without notice. the information contained herein is presented only as guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. these toshiba products are intended for usage in general electronic equipments (of?e equipment, communication equipment, measuring equipment, domestic electri?ation, etc.) please make sure that you consult with us before you use these toshiba products in equip- ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traf? signal, combustion control, all types of safety devices, etc.). toshiba cannot accept liability to any damage which may occur in case these toshiba products were used in the mentioned equipments without prior consultation with toshiba. cmos 8?it microcontrollers tmp90c800n/TMP90C801n tmp90c800f/TMP90C801f 1. outline and characteristics the tmp90c800 is a high-speed advanced 8-bit microcontroller applicable to a variety of equipment. with its 8-bit cpu, rom, ram, timer/event counter and gen- eral-purpose serial interface integrated into a single cmos chip, the tmp90c800 allows the expansion of external memories for programs and data (up to 56k bytes). the function of tmp90c800 is exactly same as the tmp90c400 except the internal rom/ram size. the TMP90C801 is the same as the tmp90c800 but without the rom. the tmp90c800n/801n is in a shrink dual inline package (sdip64-p-750). the tmp90c800f/801f is in a quad flat package (qfp64-p-1420a) the characteristics of the tmp90c800 include: (1) powerful instructions: 163 basic instructions, including multiplication, division, 16-bit arithmetic operations, bit manipulation instructions (2) minimum instruction executing time: 320ns (at 12.5mhz oscillation frequency) (3) internal rom: 8k bytes (the TMP90C801 does not have a built-in rom) (4) internal ram: 256 bytes (5) memory expansion external memory: 56k bytes (6) general-purpose serial interface (1 channel) asynchronous mode, i/o interface mode (7) 8-bit timers (4 channel): (2 external clock input) (8) port with zero-cross detection circuit (4 input) (9) input/output ports (56 pins) - ports with programmable pull-up resistor (22 pins) - allows i/o selection on bit basis - multiplexer ports of address data bus (10) interrupt function: 7 internal interrupts and 3 external interrupts (11) micro direct memory access (dma) function (8 channels) (12) standby function (4 halt modes)
2/14 toshiba corporation tmp90c800/801 figure 1. tmp90c800 block diagram
toshiba corporation 3/14 tmp90c800/801 2. pin assignment and functions this section describes the assignment of input/output pins, their names and functions. 2.1 pin assignment figure 2.1 shows pin assignment of the tmp90c800n/801n. figure 2.1 (1). pin assignment (shrink dual inline package)
4/14 toshiba corporation tmp90c800/801 figure 2.1 (2) shows pin assignment of the tmp90c800f/ 801f. figure 2.1 (2). pin assignment (flat package)
toshiba corporation 5/14 tmp90c800/801 2.2 pin names and functions the names of input/output pins and their functions are summarized in table 2.2. table 2.2 pin names and functions (1/2) pin name no. of pins i/o 3 states function p00 ~ p07 /ad0 ~ ad7 8 i/o port 0: 8-bit i/o port that allows selection of input/output on byte basis 3 states address/data bus: functions as 8-bit bidirectional address/data bus for external memory (for 401, fixed to address/data bus) p10 ~ p17 /a8 ~ a15 8 i/o port 1: 8-bit i/o port that allows selection on byte basis output address bus: functions as address bus (upper 8 bits) by ext1 set for external memory (for 401, fixed to address bus p20 ~ p23 4 i.o port 20 ~ 23: 4-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis p24 /nmi 1 i/o port 24: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis input non-maskable interrupt request pin: falling edge interrupt register pin p25 /w ait 1 i/o port 25: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis input wait: input pin for connecting slow speed memory of peripheral lsi p26 /rd 1 output port 26: 1-bit output port output read: generates strobe signal for reading external memory (for 401, fixed to rd ) p27 /wr 1 output port 27: 1-bit output port output read: generates strobe signal for writing into external memory (for 401, fixed to wr ) p30 /into 1 i/o port 30: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis input interrupt request pin 0: interrupt request pin (level/rising edge is programmable) p31 /int1 1 input port 31: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis interrupt request pin 1: rising edge interrupt request pin p32 /ti0 1 i/o port 32: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis input timer input 0: counter input pin for timer 0 p33 /ti2 1 output port 33: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis timer input 2: counter input pin for timer 2
6/14 toshiba corporation tmp90c800/801 table 2.2 pin names and functions (2/2) p35 /rxd 1 i/o port 35: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis i/o receive serial data p36 /sclk 1 i/o port 36: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis output serial clock output p37 txd 1 i/o port 37: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis output transmitter serial data p40 ~ p47 8 i/o port 4: 8-bit i/o port that allows i/o selection on bit basis p50 ~ p57 8 i/o port 5: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis p60 ~ p67 8 i/o port 6: 8-bit i/o port that allows i/o selection on bit basis ale 1 output address latch enable signal: the negative edge ale supplies an address latch timing on ad0 ~ a07 for external memory ea 1 input external access: connects with v cc pin in the tmp90c400 using internal rom, and with gnd pin in the tmp90c401 with no internal rom clk 1 output clock output: generates clock pulse at 1/4 frequency of clock oscillation. it is pulled up i nternally during resetting. reset 1 input reset: initializes the tmp90c400/401 (built-in pull-up resistor) x1/x2 2 input/output pin for quartz crystal or ceramic resonator (1 ~ 12.5mhz) v cc 1 power supply (+5v) v ss 1 ground (0v)
toshiba corporation 7/14 tmp90c800/801 3. operation this chapter describes the functions and the basic operations of the tmp90c400/401 in every block. the function of tmp90c800 is exactly same as that of tmp90c400 except the internal rom/ram size. refer to the tmp90c400 except the function which are not described this section. 3.1 cpu the tmp90c800 includes a high performance 8-bit cpu. for the function of the cpu, see the book tlcs series cpu core architecture concerning cpu operation. 3.2 memory map the tmp90c800 supports a program memory of up to 56k bytes. the program and data memory may be assigned to the address space from 0000h to ffffh. (1) internal rom the tmp90c800 internally contains an 8k-byte rom. the address space from 0000h to 1fffh is provided to the rom. the cpu starts executing a program from 0000h by resetting. the addresses 0010h to 005fh in this internal rom area are used for the entry area for the interrupt processing. the TMP90C801 does not have a built-in rom; therefore, the address space 0000h to 1fffh is used as exter- nal memory space. (2) internal ram the tmp90c800 also contains a 256-byte ram, which is allocated to the address space from ff80h to ff7fh. the cpu allows the access to a certain ram area (ff00h to ff7fh, 256 bytes) by a short operation code (opcode) in a ?irect addressing mode? the addresses from ff20h to ff5fh in this ram area can be used as parameter area for micro dma processing (and for any other purposes when the micro dma function is not used). (3) internal i/o the tmp90c800 provides a 32-byte address space as an internal i/o area, whose addresses range from ff80h to ff9fh. this i/o area can be accessed by the cpu using a short opcode in the ?irect address ing mode? figure 3.1 is a memory map indicating the areas accessible by the cpu in the respective addressing mode.
8/14 toshiba corporation tmp90c800/801 figure 3.2 (a). memory map of tmp90c800
toshiba corporation 9/14 tmp90c800/801 figure 3.2 (b). memory map of TMP90C801
10/14 toshiba corporation tmp90c800/801 4. electrical characteristics (preliminary) tmp90c800n/tmp90c800f/ TMP90C801n/TMP90C801f note: i dar is guaranteed for a total of up to 8 optional ports. 4.1 absolute maximum ratings symbol parameter rating unit v cc supply voltage -0.5 ~ + 7 v v in input voltage -0.5 ~ v cc + 0.5 v p d power dissipation (ta = 85 c) f 500 mw n 600 t solder soldering temperature (10s) 260 c t stg storage temperature -65 ~ 150 c t opr operating temperature -40 ~ 85 c 4.2 dc characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter min max unit test conditions v il input low voltage (p0) -0.3 0.8 v v il1 p1, p2, p3, p4, p5, p6 -0.3 0.3v cc v v il2 reset , nmi -0.3 0.25v cc v v il3 ea -0.3 0.3 v v il4 x1 -0.3 0.2v cc v v ih input high voltage (p0) 2.2 v cc + 0.3 v v ih1 p1, p2, p3, p4, p5, p6 0.7v cc v cc + 0.3 v v ih2 reset , nmi 0.75v cc v cc + 0.3 v v ih3 ea v cc - 0.3 v cc + 0.3 v v ih4 x1 0.8v cc v cc + 0.3 v v ol output low voltage 0.45 v i ol = 1.6ma v oh v oh1 v oh2 output high voltage 2.4 0.75v cc 0.9v cc v v v i oh = -400 m a i oh = -100 m a i oh = -20 m a i dar darlington drive current (8 i/o pins) (note) -0.1 -3.5 ma v ext = 1.5v r ext = 1.1k w i li input leakage current 0.02 (typ) 5 m a 0.0 vin v cc i lo output leakage current 0.05 (typ) 10 m a 0.2 vin v cc - 0.2 i cc operating current (run) idle 1 idle 2 20 (typ) 1.5 (typ) 6 (typ) 40 5 15 ma ma ma tosc = 10mhz (25%up @12.5mhz) stop (ta = -40 ~ 85 c) stop (ta = 0 ~ 50 c) 0.05 (typ) 50 10 m a m a 0.2 vin v cc - 0.2 v stop power down voltage (@stop) 2 ram back up 6v v il2 = 0.2v cc , v ih2 = 0.8v cc r rst reset pull up register 50 150 k w cio pin capacitance 10 pf testfreq = 1mhz v th schmitt width reset , nmi 0.4 1.0 (typ) v
toshiba corporation 11/14 tmp90c800/801 ac measuring conditions output level: high 2.2v/low 0.8v, c l = 50pf (however, cl = 100pf for ad0 ~ 7, a8 ~ 15, ale, rd , wr ) input level: high 2.4v/low 0.45v (ad0 ~ ad7) high 0.8v cc /low 0.2v cc (excluding ad0 ~ ad7) 4.3 ac characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) cl = 50pf ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t osc oscillation cycle ( = x) 80 1000 100 80 ns t cyc clk period 4x 4x 400 320 ns t wh clk high width 2x - 40 160 120 ns t wl clk low width 2x - 40 160 120 ns t al a0 ~ 7 effective address ? ale fall 0.5x - 15 35 25 ns t la ale fall ? a0 ~ 7 hold 0.5x - 15 35 25 ns t ll ale pulse width x - 40 60 40 ns t lc ale fall rd /wr fall 0.5x - 30 20 10 ns t cl rd /wr ? ale rise 0.5x - 20 30 20 ns t acl a0 ~ 7 effective address ? rd /wr fall x - 25 75 55 ns t ach upper effective address ? rd /wr fall 1.5x - 50 100 70 ns t ca rd /wr fall ? upper address hold 0.5x - 20 30 20 ns t adl a0 ~ 7 effective address ? effective data input 3.0x - 35 265 205 ns t adh upper effective address ? effective data input 3.5x - 55 295 225 ns t rd rd fall ? effective data input 2.0x - 50 150 110 ns t rr rd pulse width 2.0x - 40 160 120 ns t hr rd rise ? data hold 0 0?ns t rae rd rise ? address enable x - 15 85 65 ns t ww wr pulse width 2.0x - 40 160 120 ns t dw effective data ? wr rise 2.0x - 50 150 110 ns t wd wr rise ? effective data hold 0.5x - 10 40 30 ns t ackh upper address ? clk fall 2.5x - 50 200 150 ns t ackl lower address ? clk fall 2.0x - 50 150 110 ns t ckha clk fall ? upper address hold 1.5x - 80 70 40 ns t cck rd /wr ? clk fall x - 25 75 55 ns t ckhc clk fall ? rd /wr rise x - 60 40 20 ns t dck valid data clk fall x - 50 50 30 ns t cwa rd /wr fall ? valid wait x - 40 60 40 ns t awal lower address ? valid wait 2.0x - 70 130 90 ns t wah clk fall ? valid wait hold 0 0?ns t awah upper address ? valid wait 2.5x - 70 180 130 ns t cpw clk fall ? port data output x + 200 300 280 ns t prc port data input ? clk fall 200 200 200 ns t cpr clk fall ? port data hold 100 100 100 ns
12/14 toshiba corporation tmp90c800/801 4.4 zero-cross characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter condition min max unit v zx zero-cross detection input ac coupling c = 0.1 m f 1 1.8 vac p-p a zx zero-cross accuracy 50/60hz sine wave 135 mv f zx zero-cross detection input frequency 0.04 1 khz 4.5 serial channel timing-i/o interface mode v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) cl = 50pf ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t scy serial port clock cycle time 8x 800 640 ns t oss output data setup sclk rising edge 6x - 150 450 330 ns t ohs output data hold after sclk rising edge 2x - 120 80 40 ns t hsr input data hold after sclk rising edge 0 0?ns t srd sclk rising edge to input data valid 6x - 150 450 330 ns 4.6 8-bit event counter v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t vck ti2 clock cycle 8x + 100 900 740 ns t vckl ti2 low clock pulse width 4x + 40 440 360 ns t vckh ti2 high clock pulse width 4x + 40 440 360 ns
toshiba corporation 13/14 tmp90c800/801 4.8 i/o interface mode timing 4.7 interrupt operation v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t intal nmi , int0 low level pulse width 4x 400 320 ns t intah nmi , int0 high level pulse width 4x 400 320 ns t intbl int1, int2 low level pulse width 8x + 100 900 740 ns t intbh int1, int2 high level pulse width 8x + 100 900 740 ns
14/14 toshiba corporation tmp90c800/801 4.9 timing chart

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